module signal_input (
    input sys_clk,
    input rst_n,
    input sig_meas_i,
    input sig_test_i,
    input sig_sel_i,
    output sig_in_o
);
    reg sig_sync0, sig_sync1;
    wire sig_mux;
    assign sig_mux = sig_sel_i? sig_test_i: sig_meas_i;

    always @(posedge sys_clk, negedge rst_n) begin
        if (~rst_n) begin
            sig_sync0 <= 1'b0;
            sig_sync1 <= 1'b0;
        end else begin
            {sig_sync1, sig_sync0} <= {sig_sync0, sig_mux};
        end
    end

    assign sig_in_o = sig_sync1;

endmodule
